The present invention relates to a method for manufacturing a semiconductor device having a merged ferroelectric memory device and logic device and, more particularly, to a ferroelectric memory device manufacturing method capable of improving a topology between a ferroelectric memory device and a logic device.
In a semiconductor memory device using a ferroelectric material in a capacitor, several studies have been developed in an effort to overcome the limits of refresh in a conventional dynamic random access memory (DRAM) and to achieve large capacitance. A ferroelectric random access memory (FeRAM) is one of the nonvolatile memory devices that can store information in a powered-down downstate and has an operating speed comparable to that of the conventional DRAM.
A ferroelectric layer, such as SrBi2Ta2O9 (hereinafter, referred to as an SBT) or Pb(Zr, Ti)O3 (hereinafter, referred to as a PZT), is usually used as a capacitor dielectric in a FeRAM device. The ferroelectric layer, which is employed in a nonvolatile memory device, has a dielectric constant in a range of a few hundreds to a few thousands, and has two stabilized remnant polarization (Pr) states. The nonvolatile memory device, which uses the ferroelectric layer, has a hysteresis characteristic and inputs a digital signal xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d therein by changing an orientation of polarization according to an electric field applied to the ferroelectric layer, and stores the digital signal using a remnant polarization.
When a ferroelectric layer, such as a SrxBiy(TaiNbj)2O9 (hereinafter, referred to as an SBTN) layer, has been used besides the PZT and the SBT, then top/bottom electrodes are selected from the group consisting of Pt, Ir, Ru IrO, RuO and Pt-alloy.
In case of a merged FeRAM logic (MFeL) which merges the FeRAM and a logic device, the following process for the logic device is carried out in a smaller design rule than a normal memory manufacturing process. Therefore, after forming a capacitor, a large topology may be generated between the memory device where the capacitor is formed and the logic device. A planarization process is usually used to solve the above-mentioned problem.
FIG. 1 is a cross-sectional view illustrating a conventional merged FeRAM logic (MFeL) device. In a conventional MFeL manufacturing method, a field oxide layer 12 is formed in a predetermined portion of a semiconductor substrate 11 to separate a memory region (I) and a logic region (II), and gate electrodes 13 are formed on the semiconductor substrate 11 by depositing and patterning a polysilicon layer.
Source/drain regions 14 are formed in the semiconductor substrate 11 by inserting high density dopants therein by using the word line as a mask and a first interlayer insulating layer 15 is formed on the resulting structure of the semiconductor substrate 11. At this time, the source/drain regions 14 are formed in each of the memory region. (I) and the logic region (II), and sidewall spacers 13A are formed on each sidewall of the gate electrodes 13. The source/drain regions 14 are formed in a lightly doped drain (LDD) structure.
Next, a memory device manufacturing process is carried out in the memory region (I). A first interlayer insulating layer 15 is formed on the resulting structure of the memory device, and bit line contact holes, which expose a portion of the many source/drain regions 14, are formed by selectively patterning the interlayer insulating layer 15. A bit line 16 is formed on the resulting structure including the bit line contact hole by depositing and patterning a second polysilicon layer.
Subsequently, a second interlayer insulating layer 17 is formed on the resulting structure including the bit line 16. Plug contact holes, which expose the source/drain regions 14 of the memory region (I) except that part connected to the bit line 16, are formed by selectively patterning the second interlayer insulating layer 17. Polysilicon plugs 18 buried in the plug contact holes are formed.
As above-described, the polysilicon plugs are usually formed by depositing a third polysilicon layer and burying it in a predetermined depth of a plug contact hole using an etch back process.
Then, a barrier metal structure of TiN/TiSi2 may be formed on the polysilicon plug 18. First, a TiN/Ti layer is formed on the polysilicon plugs 18 by depositing the material on the resulting structure and carrying out a thermal process to induce reaction of a Ti material on a Si material. The resulting TiSi2 layer forms an ohmic contact between the polysilicon plugs 18 and a subsequently formed bottom electrode.
Subsequently, a bottom electrodes 19, ferroelectric layers 20 and top electrodes 21 are successively stacked up on the second interlayer insulating layer 17 including the polysilicon plugs 18. Then, a capacitor is formed by carrying out a dry etching.
Finally, a third interlayer insulating layer 22 is deposited on the resulting structure, and metal interconnection holes which expose the top electrode 21 of the capacitor are also formed by selectively etching the third interlayer insulating layer 22. At this time, the metal interconnection holes which expose the source/drain regions 14 in the logic region (II) are also formed by successively etching the third interlayer insulating layer 22, the second interlayer insulating layer 17 and the first interlayer insulating layer 15. Subsequently, metal wirings 23A and 23B, which are connected to the top electrodes 21 and the source/drain regions of the logic region (II) through each contact hole, are formed.
As above-described, in the high density ferroelectric memory device using a capacitor on bit line (COB) structure, the capacitors are formed on the plugs formed by a polysilicon.
However, when performing a dry etching process to form the capacitor, the ferroelectric layers 20 are etched with a declining width, so that a thickness of the ferroelectric layers are hardly being consistent, and there exists the limits in downsizing a capacitor.
The ferroelectric characteristic may also be decreased by a loss generated during dry etching. Moreover, when forming the third interlayer insulating layer 22 on the resulting structure after forming the capacitors, a height of the interlayer insulating layer 22 in the memory region (I) will be higher than that in the logic region (II). Consequently, a planarization process should be carried out in the following process.
It is, therefore, an object of the present invention to provide a ferroelectric memory device manufacturing method capable of overcoming the drawbacks of a dry etching of a bottom electrode to prevent a loss caused by dry etching, and obtain a uniform ferroelectric layer.
In accordance with an aspect of the present invention, there is provided a method for manufacturing a ferroelectric memory device, comprising steps of: a) forming an insulating layer on a semiconductor substrate; b) opening a capacitor region by selectively patterning the insulating layer; c) forming a bottom electrode in the opened capacitor region by using a chemical vapor deposition (CVD) method; d) forming a ferroelectric layer on an insulating layer including the bottom electrode; e) filling the ferroelectric layer on the capacitor region to a same height as that of the insulating layer surface; and f) forming a top electrode on the ferroelectric layer.
In accordance with another aspect of the present invention, there is provided a method for manufacturing a ferroelectric memory device, comprising steps of: a) forming an insulating layer on a semiconductor substrate; b) opening a bottom electrode region of a capacitor by selectively patterning the insulating layer; c) forming a bottom electrode on the opened bottom electrode region by selectively using a chemical vapor deposition (CVD) method; d) partly filling the bottom electrode region by forming a ferroelectric layer only on the bottom electrode; and forming a top electrode on the ferroelectric layer.